div_factor_freqlow_c = (c1_c/f_low)*2^width - threshold value of frequency b = 782336 div_factor_freqhigh_c = (c1_c/f_high)*2^width - threshold value of frequency a = 221184Ĭonstant div_factor_freqlow_c : integer := integer(c1_c/design_setting_g.f_low)*(2**design_setting_g.width) Signal freq_trig_s : std_logic := '0' – signal which frequency depends on the sw0 stateĬonstant c1_c : real := board_name_g.fclk/(real((2**design_setting_g.depth)*(2**design_setting_g.width))) Signal sine_ampl_s : std_logic_vector(design_setting_g.width-1 downto 0) - current amplitude value of the sine signal Signal ampl_cnt_s : std_logic_vector(design_setting_g.depth-1 downto 0) - amplitude counter Pwm_out : out std_logic - pulse width modulated signal Sw0 : in std_logic - signal made for selecting frequency User defined settings for the pwm designĬlk_p : in std_logic - differential input clock signalĬlk_n : in std_logic – differential input clock signal Adjust the modulator_pkg.vhd file to add moreĭesign_setting_g: design_setting_t := design_setting_c Possible choices: lx9_c, zedboard_c, ml605_c, kc705_c Parameter that specifies major characteristics of the board that will be used otherwise this variable will be overwritten by a upper hierarchy layerīoard_name_g : board_setting_t := kc705_c If some module is top, it needs to implement the differential clk buffer,
This_module_is_top_g : module_is_top_t := yes To create Modulator module use steps for creating modules, Sub-chapter 2.3.1 Creating a Module Using an Text Editor. design_setting_g : user defined settings for the pwm design.Adjust the modulator_pkg.vhd file to add more Possible choices: lx9_c, zedboard_c, ml605_c, kc705_c. board_name_g : parameter that specifies major characteristics of the board that will be used to implement the modulator design.this_module_is_top_g : if some module is top, it needs to implement the differential clk buffer, otherwise this variable will be overwritten by a upper hierarchy layer.sw0 : input signal from the on-board switch, used for changing output signal frequency.clk_n : differential input clock signal.